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DDR控制器MIG底层硬件逻辑：
phy_control_001文件模块解码：

`timescale 1ps / 1ps

module sip_phy_control
(
input [3:0] ao_toggle,
input [3:0] ao_wrlvl_en,
input burst_mode,
input [2:0] clk_ratio,
input [5:0] cmd_offset,
input [2:0] co_duration,
input data_ctl_a_n,
input data_ctl_b_n,
input data_ctl_c_n,
input data_ctl_d_n,
input [2:0] di_duration,
input disable_seq_match,
input [2:0] do_duration,
input [5:0] events_delay,
input [5:0] four_window_clocks,
input multi_region,
input phy_count_enable,
input [5:0] rd_cmd_offset_0,
input [5:0] rd_cmd_offset_1,
input [5:0] rd_cmd_offset_2,
input [5:0] rd_cmd_offset_3,
input [5:0] rd_duration_0,
input [5:0] rd_duration_1,
input [5:0] rd_duration_2,
input [5:0] rd_duration_3,
input spare,
input sync_mode,
input [5:0] wr_cmd_offset_0,
input [5:0] wr_cmd_offset_1,
input [5:0] wr_cmd_offset_2,
input [5:0] wr_cmd_offset_3,
input [5:0] wr_duration_0,
input [5:0] wr_duration_1,
input [5:0] wr_duration_2,
input [5:0] wr_duration_3,

output [3:0] auxoutput,
output [3:0] inburstpending,
output [1:0] inranka,
output [1:0] inrankb,
output [1:0] inrankc,
output [1:0] inrankd,
output [3:0] outburstpending,
output [1:0] pcenablecalib,
output phyctlalmostfull,
output phyctlempty,
output phyctlfull,
output phyctlready,
output [15:0] testoutput,
input memrefclk,
input phyclk,
input phyctlmstrempty,
input [31:0] phyctlwd,
input phyctlwrenable,
input plllock,
input readcalibenable,
input refdlllock,
input reset,
input scanenablen,
input syncin,
input [15:0] testinput,
input [2:0] testselect,
input writecalibenable,
input gsr
);

//protect begin

// (no unconnected output in this block)

// global signal declarations

wire _cfg_reset = global_events.cfg_reset;
wire _ghigh_b = global_events.ghigh_b;
wire _grestore = global_events.grestore;
wire _gwe = global_events.gwe;

// (no supply1 signals in this block)

// (no supply0 signals in this block)

// (no mcaddr signals in this block)

// (no mcdata signals in this block)

// interconnect signal declarations

wire [3:0] _Aux_Output_N;
wire [3:0] _In_Burst_Pending;
wire [1:0] _In_Rank_A;
wire [1:0] _In_Rank_B;
wire [1:0] _In_Rank_C;
wire [1:0] _In_Rank_D;
wire [3:0] _MC_AO_TOGGLE;
wire [3:0] _MC_AO_WRLVL_EN;
wire _MC_BURST_MODE;
wire [2:0] _MC_CLK_RATIO;
wire [5:0] _MC_CMD_OFFSET;
wire [2:0] _MC_CO_DURATION;
wire _MC_DATA_CTL_A_N;
wire _MC_DATA_CTL_B_N;
wire _MC_DATA_CTL_C_N;
wire _MC_DATA_CTL_D_N;
wire [2:0] _MC_DI_DURATION;
wire _MC_DISABLE_SEQMATCH;
wire [2:0] _MC_DO_DURATION;
wire [5:0] _MC_EVENTS_DELAY;
wire _MC_MULTI_REGION;
wire _MC_PHY_CNT_ENAB;
wire [5:0] _MC_RD_CMD_OFFSET_0;
wire [5:0] _MC_RD_CMD_OFFSET_1;
wire [5:0] _MC_RD_CMD_OFFSET_2;
wire [5:0] _MC_RD_CMD_OFFSET_3;
wire [5:0] _MC_RD_DURATION_0;
wire [5:0] _MC_RD_DURATION_1;
wire [5:0] _MC_RD_DURATION_2;
wire [5:0] _MC_RD_DURATION_3;
wire _MC_SPARE;
wire _MC_SYNC_MODE;
wire [5:0] _MC_WR_CMD_OFFSET_0;
wire [5:0] _MC_WR_CMD_OFFSET_1;
wire [5:0] _MC_WR_CMD_OFFSET_2;
wire [5:0] _MC_WR_CMD_OFFSET_3;
wire [5:0] _MC_WR_DURATION_0;
wire [5:0] _MC_WR_DURATION_1;
wire [5:0] _MC_WR_DURATION_2;
wire [5:0] _MC_WR_DURATION_3;
wire [5:0] _MC_4WINDOW_CLKS;
wire _Mem_Ref_Clk;
wire [3:0] _Out_Burst_Pending;
wire [1:0] _PC_Enable_Calib;
wire _PHY_Clk;
wire _PHY_Ctl_AlmostFull_N;
wire _PHY_Ctl_Empty;
wire _PHY_Ctl_Full_N;
wire _PHY_Ctl_Mstr_Empty;
wire _PHY_Ctl_Ready_N;
wire [31:0] _PHY_Ctl_Wd;
wire _PHY_Ctl_Wr_Enable;
wire _PLL_Lock;
wire _Read_Calib_Enable;
wire _RefDLL_Lock;
wire _Reset;
wire _Scan_Enable_N;
wire _Sync_In;
wire [15:0] _Test_Input;
wire [15:0]